ASIC/Layout Design Engr II
Synopsys
0 - 0 Years
|
Confidential
|
Hyderabad
Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. These breakthroughs are ushering in the era of Smart Everything-where devices are getting smarter, everything is connected, and everything must be secure.
Powering this new era of digital innovation are high-performance silicon chips and exponentially growing amounts of software content. Synopsys is at the forefront of Smart Everything with the world's most advanced technologies for chip design, verification, IP integration, and software security and quality testing. We help our customers innovate from silicon to software so they can bring Smart Everything to life.
Website: www.synopsys.com
Profile Offered: ASIC/Layout Design Engr II
Job location: Hyderabad
Course Specialization: ME/M.Tech, Other Course, BE/B.Tech
Desired Experience: 0 - 3 Years
Requirements:
In-depth familiarity with the layout of analog and mixed-signal CMOS circuits.
Exposure to Analog/Mixed-signal circuit layouts (ie. RX, TX, PLL, etc...).
Knowledge of signal integrity issues (ie. clock/data routes, differential routing, shielding).
Aware of layout techniques to mitigate ESD, latch-up.
Familiarity with the custom digital layout (ie. high-speed logic paths).
Knowledge of design for reliability (ie. EM, IR, etc...).
Knowledge of layout effects (ie. matching, reliability, proximity effects, spacing effects etc...).
Knowledge of advanced FinFET nodes (7nM and below).
Tools: Custom Compiler, ICV, Calibre, Star-RCXT, etc.
Exposure to scripting (ie. TCL, PERL, etc...).
Education:
B.Tech/B.E., Diploma 3 Yr., M.Tech./M.E.
Work Experience:
0 - 0 Years
Salary
Confidential
Industry
Real Estate/Infrastructure/Construction
